In the field integrated circuit (IC) memory, improving the bit-density of a memory has been a goal for numerous reasons, including reduction of cost and size, and improvement in productivity. One tactic is to decrease the size of an individual memory cell. A second is to add a third dimension (multiple layers) to conventional two-dimensional (planar) structures. However, cells are approaching geometric limits, and further dramatic reductions of memory cell size are unlikely with conventional memory cell design style as evidenced by its long history of multiple small, incremental improvements over the past three decades.
Conventional memory cells contain at least one transistor, two access ports, and one or more control ports. The need for a transistor (or transistors) with their accompanying control port(s) places severe restrictions on future improvements in memory density. First, the ability to reduce cell size further through design innovation is limited because cell size has become largely dependent on improvements in lithographic and fabrication techniques. Second, the option to add multiple cell layers is forfeited because modern IC technologies can currently only place good quality transistors (required in transistor based memory cells) in a single layer, the substrate.
Another approach taken by the prior art in U.S. Pat. No. 6,185,122 has been to use a memory cell comprising a current steering element in series with a state change element, eliminating the need for one or more transistors within the memory cell. This arrangement allows placement of memory cells in multiple layers above the substrate as long as a suitable current steering element (such as a diode) is available for the memory cell. Essentially, conductors are arranged in a grid of multiple layers with memory cells placed at the intersections of orthogonal conductors in adjacent layers. While this offers a substantial improvement by the addition of memory cells in multiple vertical layers, restrictions are placed either on the type of conductor material or the current steering element in the memory cell or both to achieve the most easily manufactured solution.
This invention describes a different approach to overcome past limitations by employing memory cells that do not require any transistors or current steering mechanism but are simple, extremely small interconnect—only two-terminal cells. The memory cell state, bit state 0 or bit state 1, is denoted by the resistance level of the cell either high or low, and is accessed by a conductor with controllable conductance states. This structure can be formed as a multiple layer array above the substrate with extremely high bit densities yet its bit states are accessible with small and efficient circuitry outside the array.